Pipeline FP RISC-V: an interactive simulator for teaching computer architecture
I have released Pipeline FP RISC-V, a free web simulator of an in-order RISC-V pipeline with multicycle floating-point units, following Chapter 3 and Appendix C of Computer Architecture: A Quantitative Approach (7th edition) by Hennessy, Patterson and Kozyrakis.
It shows the full cycle diagram of a program, or lets you step through it cycle by cycle, highlighting RAW, structural and WAW stalls and branch freezes, along with cycles, CPI and stalls by type. It is available in English and Spanish, and runs directly in the browser.
